This invention relates to semiconductor devices and more particularly to a novel field effect transistor (FET) device and accompanying logic circuit that is multifunctional and selectively operates in two different modes, including in a mode that exhibits negative differential resistance (NDR). The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for logic applications where it is desirable to achieve a high level of functional integration using multi-functional devices that can perform multiple boolean operations and/or multiple circuit operations.
A new type of CMOS compatible, NDR capable FET is described in the aforementioned applications to King et al. referenced above. The advantages of such device are well set out in such materials, and are not repeated here. Nonetheless, in some environments, or during certain processing operations, it may be desirable to selectively disable the NDR capability of such device, and instead operate such device in a manner similar to that for any other conventional FET. This selective switching between modes is not practically possible with prior art NDR implementations (such as tunnel diodes for example) but if such were available it would make it feasible nonetheless to construct a multi-mode, multi-functional device. In other words, a single device could be constructed to perform more than one logical operation on one or more signal inputs. An improved device shown in U.S. Pat. No. 6,097,036 (incorporated by reference herein) details how a single semiconductor logic element can be constructed to perform more than one logic operation using a tunneling effect, but the latter mechanism is typically implemented with a GaAs (non-CMOS compatible) manufacturing process that is unattractive for mainstream semiconductor fabrication facilities. A similar limitation is apparent for the traditional resonant tunneling diode (RTD) based devices as depicted for example in FIG. 3 of a reference from the Microelectronics Advanced Research Initiative entitled xe2x80x9cResonant Tunnelling Device Logic Circuitsxe2x80x9d Technical Report July 1998xe2x80x94July 1999 by Pascha et al., the entirety of which is incorporated herein. This reference illustrates a typical example of a monostablexe2x80x94bistable RTD inverter whose output varies depending on the state of an input clock. In other words, it can selectively induce an NDR effect in a tunneling diode so that in a non-NDR operating region the circuit has one type of output (linear or monostable) while in an NDR operating region the circuit has a bistable output. While this circuit is useful for large scale integrated logic circuits, it would be more useful to have an NDR device in which the actual NDR effect itself can be selectively enabled or disabled, so that in a non-NDR mode a device will not enter into an NDR operating region even with operating parameters which would otherwise be expected to induce such NDR effect.
Accordingly, an object of one aspect of the present invention is to provide an improved multi-mode FET that can be selectively controlled to operate in either an NDR mode or an non-NDR mode;
A related object of another aspect of the invention is to provide an improved multi-mode logic circuit employing the aforementioned multi-mode FET, and which can be programmed to perform two distinct logic operations, including a first type of logic operation in an NDR mode, and a second type of logic operation in a non-NDR mode;
A further object of the invention is to provide an improved multi-mode logic circuit that can be programmed and/or adjusted to perform two different boolean logic operations on a set of inputs, and/or two different circuit operations for a variable input;
A related object of the present invention is to provide a multi-terminal structure for controlling and programming the aforementioned multi-mode FET and/or multi-mode logic circuit, including the type of logic operation to be performed;
Yet another object of the present invention is to provide a new programmable logic FET which can be fabricated with a process that is fully compatible with conventional CMOS process technology, and yet be able to simultaneously provide more than one logical operation or function;
Another object of the present invention is to provide an improved multi-mode FET that is not based on heterostructure materials, or expensive fabrication techniques such as molecular beam epitaxy (MBE);
Another object of the present invention is to provide a new type of electronic logic circuit or logic family that can supplement and/or replace conventional semiconductor FET logic families, and in so doing effectuate new embodiments of common but critical logic circuits that are smaller, faster and more easily integrated;
Another object of the present invention is to introduce a new type of electronic logic family that has a number of useful characteristics and capabilities, including controlled programmable and re-programmable functionality at the single device level, and multiple simultaneous functionality, so that a new CMOS compatible logic building block can be provided for higher scale integrated circuits used in digital signal processors (DSPs) microprocessors, etc with a reduced gate count per logic function;
A further object of the invention is to provide a cost effective and reliable manufacturing method for making the aforementioned multi-mode FET and logic circuit, preferably using CMOS compatible processes that are easily integrable into commercial fabrication facilities.
These and other objects are achieved by the present invention that discloses an electronic device having a semiconductor structure adapted to selectively operate in a negative differential resistance mode through the use of a terminal coupled to a region of the semiconductor structure for receiving a mode selection signal. This mode selection signal selects whether the negative differential resistance mode is enabled or disabled; i.e., whether the device can exhibit NDR characteristics, or is limited to conventional FET characteristics. In a preferred embodiment, the semiconductor structure is substantially that of a four terminal FET that operates selectively in an NDR mode or a non-NDR mode through control of a bias signal applied to one of such terminals (e.g., a body terminal contact). The negative differential resistance mode is caused within a single semiconducting channel of the semiconductor structure at least in part by temporary electron trapping within a gate dielectric of the semiconductor structure. Stated another way, a negative differential resistance mode is created at least in part by dynamically varying the threshold voltage of the FET. The threshold voltage is adjusted by selectively removing hot carriers within the channel so as to set up a depletion region for reducing current carrier density in the channel. A trapping layer, adjacent to the channel, is used for temporarily trapping a sufficient number of carriers to cause the negative differential resistance mode.
The semiconductor structure is manufactured using standard complementary metal oxide semiconductor (CMOS) fabrication processes, including conventional masking, patterning, etching, thermal oxidation, implant, annealing, thermal treatment and deposition techniques normally used for making semiconductor devices. A multi-mode field effect transistor (FET) device is thus constructed through such processes to include: a first region configured as a source for the FET; a second region configured as a drain for the FET; and a third region configured to serve as a gate for the FET. The source and drain are coupled by a channel region which can be selectively controlled, under a suitable bias condition applied to the gate, to have a first negative differential resistance mode, or a second non-negative differential resistance mode. A fourth region acts as a body for the FET, and is configured to receive the aforementioned mode select signal. Thus, the structure is preferably formed of materials located in or on a silicon based substrate.
The mode selection signal can be varied as well by a control circuit so that the semiconductor structure is dynamically programmable to a negative differential resistance mode or a non-negative differential resistance mode. With this type of configuration, a semiconductor structure can cause a first circuit function to be performed on an input signal when a negative differential resistance mode for such structure is enabled, or alternatively cause a second circuit function to be performed on the input signal when the negative differential resistance mode is disabled. The non-negative differential resistance mode could be employed by the semiconductor structure to store configuration information for a larger device. In addition to a multi-mode circuit function on a single input, the semiconductor structure can also cause a first boolean operation to be performed on a set of input signals when the negative differential resistance mode is enabled, or alternatively it can cause a second boolean operation to be performed on the input signal when the negative differential resistance mode is disabled.
A larger multi-element multi-mode electronic circuit can be constructed using one or more of the aforementioned semiconductor structure elements as a building block, along with optional additional conventional FET and/or passive semiconductor elements. Thus, such circuit includes at least one first type semiconductor structure adapted to selectively operate in a negative differential resistance mode as noted earlier. A second type semiconductor structure is coupled to the at least one first type semiconductor structure; this second type semiconductor is preferably comprised of conventional semiconductor elements and is thus adapted to operate only in a non-negative differential resistance mode.
In this fashion, the multi-mode electronic circuit performs a first circuit function on an input signal when the negative differential resistance mode is enabled, and a second circuit function on input signal when the negative differential resistance mode is disabled. For example, a first circuit function could be an inverter function, while a second circuit function could be a fixed voltage output (usable as a set or reset signal or to store configuration information).
When multiple inputs are desirable (such as for performing a logic operation), the circuit is thus capable of performing a first -boolean operation when the negative differential resistance mode is enabled, and a second boolean operation when the negative differential resistance mode is disabled. In a preferred embodiment, the first Boolean operation is an XNOR function, and the second Boolean operation is a NOR function. As above, the mode selection signal can be varied during operation of the multi-mode electronic circuit to dynamically change the logic operation as needed to effectuate the desired logic function. In this fashion, a true programmable logic block or: processing engine can be constructed that multi-tasks because it can perform the same functionality as the equivalent of two prior art circuits but in less than half the space. Using one easily measurable metric, it is apparent that the invention affords a function/element ratio greater than 0.5, and approaching 1.
A method of operating the aforementioned multi-mode electronic device generally includes the following steps: operating a semiconductor structure in a first mode characterized by negative differential resistance in at least one operating region of the structure; and operating the semiconductor structure in a second mode characterized by a non-negative differential resistance in such operating region; and coupling a region of the semiconductor structure to a mode selection signal; and selecting whether the first mode or the second mode is enabled for said semiconductor structure using the mode selection signal.